This invention relates to a parallel type A/D converter capable of converting an analog value into a digital value.
In a conventional parallel type A/D converter, as shown in FIG. 1, an input signal 1 is fed parallel to one input end of each of the comparators which compose the comparator chain 4. A standard voltage 2 is divided by a standard resistor chain 3 composed of resistors R1 to R16, and individual reference voltages Vr1 to Vr15 are thus formed. These reference voltages are respectively and sequentially fed into the other input end b of each of the comparators C1 to C15. The individual comparators C1 to C15 compare the individual reference voltages Vr1 to Vr15 with the input signal 1, and amplify and deliver the results of the comparison to output ends c. The output level of the output ends c is either "1" or "0", depending on whether or not the input signal 1 is higher than the reference voltage inputted at each comparator C1 to C15. Accordingly, logic circuits L1 to L15 composing a logic circuit chain 5, have as inputs non-inverted logic signals from a corresponding comparator and inverted logic signals from an adjacent comparator to obtain an AND of those signals i.e., the logic output of a logic circuit receiving two different input signals becomes "1, " while the logic outputs of the other logic circuits become 0. Accordingly, this logic output is entered into an encoder circuit 6, and only the activated code is selected. Consequently a binary output is delivered to an output end 7, to thereby perform the analog-to-digital conversion effectively.
In such a parallel type A/D converter, when one of the reference voltages Vr1 to VR15 applied to comparators C1 to C15 and the input voltage 1 signal voltage are extremely close to each other, an error is caused, and the reliability of the A/D conversion is extremely impaired.
This problem is explained by referring to diagrams. FIG. 2 shows the input and output characteristics of the comparator circuits. The comparators generate an output voltage having a logic level of 1 when the input signal is higher than the reference voltage, and an output voltage having a logic level of 0 when the input signal is lower than the reference voltage, and also generate a voltage close to the logic threshold value when the input signal is close to the reference voltage. In this condition, due to hysteresis characteristics noise, and the logic level falls into an ambiguous state. FIG. 3 is a logic circuit diagram showing a portion of the conventional parallel type A/D converter shown in FIG. 1. Supposing the input of the logic circuits in the logic circuit chain 5 to be A and the inverted input to be B, the logic circuit output Q is expressed in a logic formula of EQU Q=A.multidot.B (1)
FIG. 4A, 4B, and 4C are logic state diagrams representing the input and output states of these logic circuits, in which i, i-1, i-2 denote the logic circuit numbers. When the input signal 1 is sufficiently higher than the reference voltage Vri-1 of the comparator number i-1 and is lower than the reference voltage Vri of the comparator number i, the logic state becomes as shown in FIG. 4A, and only the logic output Q of the logic circuit number i-1, L(i-1) becomes 0 while other logic outputs are all 0, so that a binary normal converted value is obtained in the encoder circuit 7 shown in FIG. 1. However, when the input signal becomes nearly equal to the reference voltage Vri, the following two errors may occur. FIG. 4B shows a case in which the output signal from the comparator number i is so near the logic threshold value that it is regarded as 0 in the logic circuit number i-1 and as 1 in the logic circuit number i. Consequently, two logic outputs become 1 And an error results in the encoder circuit 6. For example, when the logic circuits number 7 and number 8 generate 1, in the encoder circuit 6, "0111" and "1000" are combined in an OR operation in each bit on the encoder, and "1111" or "15" is delivered, which is a very large error compared to the true value of "7" or "8." In FIG. 4C, contrary to FIG. 4B, the output signal from the comparator number i is regarded as 0 in the logic circuit number i-1, and as 1 in the logic circuit number i, and in this condition all logic outputs are 0, which also results in a significant error.
Thus, the conventional parallel type A/D converter, the intrinsic tendency of creating an error as pointed out in a paper by Bernhard Zojer et al. (A 6-bit/ 200-MHz full nyquist A/D converter, IEEE J. Solid-State Circuits, vol. sc-20, No. 3, pp. 780-786, June 1985).
The relation between this error occurrence probability P.epsilon. and the conversion time is expressed as EQU P.epsilon.=(Va/Vq)exp(-.tau./.tau.) (2)
where Va is an input ambiguous voltage of the comparator, Vq is a unit quantization voltage, t is the duration of the strobing mode of the comparator which is usually half the conversion time, and .tau. is a time constant of the strobe circuit.
Accordingly, in an ordinary parallel type A/D converter, as the conversion rate is increased, the error incidence rate becomes higher, which is thereby creating a bottle-neck for high speed conversion.